This invention relates generally to fault testing of integrated logic circuits, and more particularly the invention relates to test pattern generation using a transformed circuit description to facilitate the generation of the test pattern.
Present day very large scale integrated (VLSI) logic circuits typically contain many thousands of circuit elements. Since not all fabricated circuits are guaranteed to be fault-free, testing needs to be done to isolate fault-free from faulty circuits. It has been estimated that the cost of detecting and replacing a faulty integrated circuit increases by a factor of 10 with each level of packaging, i.e., chip--printed circuit board--system employing multiple printed circuit boards. Thus, the detection of a faulty chip prior to further packaging is of great importance.
Manufacturing test sets are applied to detect the presence of physical faults which render incorrect operation of the circuit. One measure of the completeness of a manufacturing test set is the percentage of defects (physical faults) which it is able to detect. Most defects can be represented as logical faults. Since the effects of these logical faults on the behavior of the circuit are well defined, a test for a physical fault can be derived based upon the difference in the operation of the circuit in both the presence and absence of the fault. Since all possible faults can be enumerated, the completeness (quality) of the manufacturing test set can be calculated as the percentage of the total number of faults which a test set detects. The ultimate metric of quality of a manufacturing test set is the escape rate, that being the percentage of faulty circuits which are not detected as such. In general, the larger the fault coverage the higher the resultant test quality of a manufacturing test set.
Manufacturing test sets or test patterns for integrated circuit testing can be generated manually or by using Automated Test Pattern Generation (ATPG) software, such as HITEC, which is a commercially available system that runs on commercially available workstations. The test patterns are usually generated based on a structural description of the circuit in which the circuit is described as a connection of basic elements such as logic gates (e.g., AND, OR, NOT). In addition to the quality of a test set which an ATPG is able to produce, the time required for the ATPG to generate a test set is an important measure of the effectiveness of the ATPG. While test patterns which detect nearly all faults can be generated in a reasonable amount of time for large combinational circuits given only a structural description of the circuit, none of the existing test pattern generation algorithms based on a structural description of a sequential circuit can generate a high quality test set in a reasonable amount of time for large sequential circuits. Generating a test set for a sequential circuit requires identifying a sequence of values to be applied during multiple clock periods to the functional inputs of the circuit. The multiple clock periods are required for a signal to propagate from the functional inputs to the functional outputs in the sequential circuit. The interdependency of logic values at various internal nodes of the circuit across time frames is the primary reason for the increasing complexity of sequential circuit test generation.
Since ATPG systems are typically unable to create manufacturing test sets which attain reasonable levels of test quality for most industrial sequential circuits, circuit structures are often altered to provide increased controllability and observability of internal nodes of the circuit.
Two of the most commonly used techniques of altering the structure of sequential circuits to reduce the difficulty of generating manufacturing test sets are the so-called full scan or partial scan techniques such as described in Trischler U.S. Pat. No. 4,534,028 and Agrawal U.S. Pat. No. 4,493,077. In scan testing, test control circuitry is included as part of the logic of a chip. This circuitry provides increased controllability and observability of sequential elements of the circuit, thus simplifying the task of generating the manufacturing test set. While full scan and partial scan techniques provide the benefits of increasing the level of fault coverage which an ATPG can attain and decreasing the amount of time required to generate the manufacturing test set, implementation of the techniques increases the circuit chip area and decreases the circuit operating speed.
The present invention is directed to providing an improved method and apparatus for automated test pattern generation for sequential logic circuits without a need for increasing silicon area or performance loss.